Lithographic alignment of a conductive line to a via
US10685879B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Aug 15, 2019 |
| Grant date | Jun 16, 2020 |
| Priority date | — |
| Expiry date | Aug 15, 2039 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L23/5283
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method for fabricating a semiconductor device includes forming misalignment tolerant vias each having a landing area configured to account for alignment mismatch resulting from subsequent formation of conductive structures, depositing a conductive layer over the misalignment tolerant vias, and obtaining conductive layer patterning including each of the conductive structures formed on at least a portion of a respective one of the landing areas, including subtractively patterning the conductive layer. The misalignment tolerant vias and the conductive structures imparting a semiconductor device geometry accounting for the alignment mismatch.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.