Ashim Dutta
82Patents
4h-index
58Co-inventors
65Inventor score
Filing activity: Jul 1, 2014 → Jul 13, 2023
Most-cited inventions
| Patent | Title | Area | Cited by | Status |
|---|---|---|---|---|
| US10707413B1 | Formation of embedded magnetic random-access memory devices | Electricity | 19 | Active |
| US10879107B2 | Method of forming barrier free contact for metal interconnects | Electricity | 9 | Active |
| US10833257B1 | Formation of embedded magnetic random-access memory devices with multi-level bottom electrode via contacts | Electricity | 7 | Active |
| US10957850B2 | Multi-layer encapsulation to enable endpoint-based process control for embedded memory fabrication | Electricity | 4 | Active |
| US11223008B2 | Pillar-based memory hardmask smoothing and stress reduction | Electricity | 4 | Active |
| US10685879B1 | Lithographic alignment of a conductive line to a via | Electricity | 4 | Active |
| US10833258B1 | MRAM device formation with in-situ encapsulation | Electricity | 3 | Active |
| US10672611B2 | Hardmask stress, grain, and structure engineering for advanced memory applications | Electricity | 2 | Active |
| US9679852B2 | Semiconductor constructions | Electricity | 2 | Active |
| US11502242B2 | Embedded memory devices | Electricity | 1 | Active |
| US11227892B2 | MRAM integration with BEOL interconnect including top via | Electricity | 1 | Active |
| US9984977B2 | Semiconductor constructions | Electricity | 1 | Active |
| US11437083B2 | Two-bit magnetoresistive random-access memory device architecture | Electricity | 1 | Active |
| US11744083B2 | Fabrication of embedded memory devices utilizing a self assembled monolayer | Electricity | 1 | Active |
| US10796911B2 | Hardmask stress, grain, and structure engineering for advanced memory applications | Electricity | 1 | Active |
| US10615037B2 | Tone reversal during EUV pattern transfer using surface active layer assisted selective deposition | Electricity | 1 | Active |
| US10672618B2 | Systems and methods for patterning features in tantalum nitride (TaN) layer | Electricity | 1 | Active |
| US11495538B2 | Fully aligned via for interconnect | Electricity | 1 | Active |
| US11121173B2 | Preserving underlying dielectric layer during MRAM device formation | Electricity | 1 | Active |
| US12183630B2 | Additive interconnect formation | Electricity | 0 | Active |
| US12327770B2 | Probe pad with built-in interconnect structure | Electricity | 0 | Active |
| US11205678B2 | Embedded MRAM device with top via | Electricity | 0 | Active |
| US11189783B2 | Embedded MRAM device formation with self-aligned dielectric cap | Electricity | 0 | Active |
| US11189561B2 | Placing top vias at line ends by selective growth of via mask from line cut dielectric | Electricity | 0 | Active |
| US11158786B2 | MRAM device formation with controlled ion beam etch of MTJ | Electricity | 0 | Active |
Source: USPTO / EPO open patent data. Inventor disambiguation is heuristic; counts are objective bibliographic measures.