Method for incorporating multiple channel materials in a complimentary field effective transistor (CFET) device
US10685887B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Nov 29, 2018 |
| Grant date | Jun 16, 2020 |
| Priority date | — |
| Expiry date | Nov 29, 2038 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D30/797
- WIPO fieldMicro-structural and nano-technology
- WIPO sectorChemistry
Abstract
A method of manufacturing a semiconductor device includes: providing a substrate having a base fin structure thereon, the base fin structure including a first stacked portion for forming a channel of a first gate-all-around (GAA) transistor, the first stacked portion including a first channel material, a second stacked portion for forming a channel of a second GAA transistor, the second stacked portion including second channel material, and a sacrificial portion separating the first stack portion from the second stack portion, wherein the first channel material, the second channel material and the sacrificial material have different chemical compositions from each other; exposing the side of the base fin structure to an isotropic etch process which selectively etches one of the first channel material, the second channel material and the sacrificial material; and forming first and second GAA gate structures around said first channel material and said second channel material respectively.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.