Semiconductor chip package with resilient conductive paste post and fabrication method thereof
US10685943B2 · kind B2 · utility
0Cited by
8References
14Claims
0Family size
Assignee
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Key dates
| Filing date | Sep 12, 2017 |
| Grant date | Jun 16, 2020 |
| Priority date | — |
| Expiry date | Sep 12, 2037 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/35121
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A semiconductor chip package includes a substrate; a semiconductor die mounted on the substrate, wherein the semiconductor die comprises a bond pad disposed on an active surface of the semiconductor die, and a passivation layer covering perimeter of the bond pad, wherein a bond pad opening in the passivation layer exposes a central area of the bond pad; a conductive paste post printed on the exposed central area of the bond pad; and a bonding wire secured to a top surface of the conductive paste post. The conductive paste post comprises copper paste.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.