Contact formation in semiconductor devices
US10685961B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Mar 27, 2019 |
| Grant date | Jun 16, 2020 |
| Priority date | — |
| Expiry date | Mar 27, 2039 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D64/017
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A technique relates to fabricating a pFET device and nFET device. A contact trench is formed through an inter-level dielectric layer (ILD) and a spacer layer. The ILD is formed over the spacer layer. The contact trench exposes a p-type source/drain region of the pFET and exposes an n-type source/drain region of the NFET. A gate stack is included within the spacer layer. A p-type alloyed layer is formed on top of the p-type source/drain region in the pFET and on top of the n-type source/drain region of the nFET. The p-type alloyed layer on top of the n-type source/drain region of the nFET is converted into a metallic alloyed layer. A metallic liner layer is formed in the contact trench such that the metallic liner layer is on top of the p-type alloyed layer of the pFET and on top of the metallic alloyed layer of the nFET.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.