Implantations for forming source/drain regions of different transistors
US10685967B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | May 20, 2019 |
| Grant date | Jun 16, 2020 |
| Priority date | — |
| Expiry date | May 20, 2039 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D84/859
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method includes forming a first transistor including forming a first gate stack, epitaxially growing a first source/drain region on a side of the first gate stack, and performing a first implantation to implant the first source/drain region. The method further includes forming a second transistor including forming a second gate stack, forming a second gate spacer on a sidewall of the second gate stack, epitaxially growing a second source/drain region on a side of the second gate stack, and performing a second implantation to implant the second source/drain region. An inter-layer dielectric is formed to cover the first source/drain region and the second source/drain region. The first implantation is performed before the inter-layer dielectric is formed, and the second implantation is performed after the inter-layer dielectric is formed.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.