Clock phase compensation apparatus and method
US10686582B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Feb 25, 2019 |
| Grant date | Jun 16, 2020 |
| Priority date | — |
| Expiry date | Feb 25, 2039 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K2005/00019
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
An apparatus and method is provided that compensates for the supply droops to minimize strobe shifts and to regain eye margin. The apparatus includes a droop detector to detect voltage droops at one or more trip (or threshold) levels and these detected voltage droops are translated to a shift in clock phase setting. For example, propagation delay of a delay locked loop (DLL) and/or clock edge selection from a phase interpolator (PI) is adjusted according to the detected voltage droop levels to maintain a trained relationship between the sampling clock strobe and data eye. A lookup table is used to determine a PI code or a DLL propagation delay code corresponding to a voltage droop level.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.