Inventor · San Jose, CA, US

Gerald Pasdast

43Patents
7h-index
74Co-inventors
72Inventor score

Filing activity: Sep 30, 1999 → Apr 5, 2024

Most-cited inventions

PatentTitleAreaCited byStatus
US6326802A On-die adaptive arrangements for continuous process, voltage and temperature compensation Electricity 23 Expired
US10686582B1 Clock phase compensation apparatus and method Electricity 12 Active
US10552357B2 Multichip package link Emerging Cross-Sectional Technologies 12 Active
US11581282B2 Serializer-deserializer die for high speed signal interconnect Electricity 10 Active
US9692402B2 Method, apparatus, system for centering in a high performance interconnect Electricity 9 Active
US10795853B2 Multiple dies hardware processors and methods Emerging Cross-Sectional Technologies 8 Active
US10073808B2 Multichip package link Emerging Cross-Sectional Technologies 8 Active
US9946676B2 Multichip package link Physics 7 Active
US11652059B2 Composite interposer structure and method of providing same Electricity 3 Active
US11094672B2 Composite IC chips including a chiplet embedded within metallization layers of a host IC chip Electricity 3 Active
US11270947B2 Composite interposer structure and method of providing same Electricity 3 Active
US12107060B2 Microelectronic assemblies with inductors in direct bonding regions Electricity 3 Active
US12062631B2 Microelectronic assemblies with inductors in direct bonding regions Electricity 2 Active
US12117960B2 Approximate data bus inversion technique for latency sensitive applications Physics 1 Active
US11003610B2 Multichip package link Emerging Cross-Sectional Technologies 1 Active
US12159840B2 Scalable and interoperable PHYLESS die-to-die IO solution Electricity 0 Active
US11586579B2 Multiple dies hardware processors and methods Emerging Cross-Sectional Technologies 0 Active
US12164319B2 Dual loop voltage regulator Physics 0 Active
US11294852B2 Multiple dies hardware processors and methods Emerging Cross-Sectional Technologies 0 Active
US12315794B2 Skip level vias in metallization layers for integrated circuit devices Electricity 0 Active
US11205630B2 Vias in composite IC chip structures Electricity 0 Active
US11367707B2 Semiconductor package or structure with dual-sided interposers and memory Electricity 0 Active
US12362306B2 Clock-gating in die-to-die (D2D) interconnects Electricity 0 Active
US12014990B2 Composite interposer structure and method of providing same Electricity 0 Active
US11694986B2 Vias in composite IC chip structures Electricity 0 Active

Source: USPTO / EPO open patent data. Inventor disambiguation is heuristic; counts are objective bibliographic measures.