Multi-level signaling in memory with wide system interface
US10686634B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Aug 8, 2019 |
| Grant date | Jun 16, 2020 |
| Priority date | — |
| Expiry date | Aug 8, 2039 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L25/4921
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Techniques are provided herein to increase a rate of data transfer across a large number of channels in a memory device using multi-level signaling. Such multi-level signaling may be configured to increase a data transfer rate without increasing the frequency of data transfer and/or a transmit power of the communicated data. An example of multi-level signaling scheme may be pulse amplitude modulation (PAM). Each unique symbol of the multi-level signal may be configured to represent a plurality of bits of data.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.