Methods and systems for efficient identification of glitch failures in integrated circuits
US10690722B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Feb 8, 2019 |
| Grant date | Jun 23, 2020 |
| Priority date | — |
| Expiry date | Feb 10, 2039 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2119/22
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Methods and systems are described to efficiently identify the potential for failures in integrated circuits (ICs) caused by glitches. In an IC based on synchronous operation, the operation of the multiplicity of inputs, storage elements and observed outputs in said IC are synchronized to one or more clocks that determine the specific times at which inputs change, outputs are observed, and stored values are updated. Almost all ICs are based on synchronous operation. When input values to a logic circuit in an IC change, the effects of said changes propagate through paths in said logic circuit in a delayed manner such that each of said paths may have a different delay. Said different delays can cause a wire in a logic circuit to have transient values (termed “glitch”) before settling to a final value consistent with the input values being applied to said logic circuit. An IC is likely to function erroneously, referred to as having a “glitch failure”, when a glitch value is observed at an output or captured by a storage element. Glitch failures are difficult and expensive to diagnose in a manufactured IC. To raise the productivity of IC development, it is imperative that any potential …
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.