Hari Mony
97Patents
8h-index
27Co-inventors
74Inventor score
Filing activity: Feb 20, 2003 → Feb 8, 2019
Most-cited inventions
| Patent | Title | Area | Cited by | Status |
|---|---|---|---|---|
| US7882473B2 | Sequential equivalence checking for asynchronous verification | Physics | 27 | Active |
| US7299432B2 | Method for preserving constraints during sequential reparameterization | Physics | 19 | Expired |
| US7260799B2 | Exploiting suspected redundancy for enhanced design verification | Physics | 15 | Expired |
| US7367002B2 | Method and system for parametric reduction of sequential designs | Physics | 12 | Expired |
| US8181134B2 | Techniques for performing conditional sequential equivalence checking of an integrated circuit logic design | Physics | 11 | Active |
| US7322017B2 | Method for verification using reachability overapproximation | Physics | 10 | Expired |
| US7448005B2 | Method and system for performing utilization of traces for incremental refinement in coupling a structural overapproximation algorithm and a satisfiability solver | Physics | 10 | Active |
| US7266795B2 | System and method for engine-controlled case splitting within multiple-engine based verification framework | Physics | 9 | Expired |
| US7203915B2 | Method for retiming in the presence of verification constraints | Physics | 8 | Expired |
| US7315996B2 | Method and system for performing heuristic constraint simplification | Physics | 8 | Expired |
| US7437690B2 | Method for predicate-based compositional minimization in a verification environment | Physics | 8 | Active |
| US7890901B2 | Method and system for verifying the equivalence of digital circuits | Physics | 7 | Active |
| US7356792B2 | Method and system for enhanced verification by closely coupling a structural overapproximation algorithm and a structural satisfiability solver | Physics | 7 | Expired |
| US7934180B2 | Incremental speculative merging | Physics | 7 | Active |
| US7421669B2 | Using constraints in design verification | Physics | 7 | Expired |
| US7779378B2 | Computer program product for extending incremental verification of circuit design to encompass verification restraints | Physics | 7 | Active |
| US8146034B2 | Efficient Redundancy Identification, Redundancy Removal, and Sequential Equivalence Checking within Designs Including Memory Arrays. | Physics | 7 | Active |
| US7380222B2 | Method and system for performing minimization of input count during structural netlist overapproximation | Physics | 7 | Expired |
| US6993734B2 | Use of time step information in a design verification system | Physics | 6 | Expired |
| US7350169B2 | Method and system for enhanced verification through structural target decomposition | Physics | 6 | Expired |
| US7475370B2 | System for verification using reachability overapproximation | Physics | 6 | Active |
| US8578311B1 | Method and system for optimal diameter bounding of designs with complex feed-forward components | Physics | 6 | Active |
| US7509605B2 | Extending incremental verification of circuit design to encompass verification restraints | Physics | 6 | Active |
| US8589837B1 | Constructing inductive counterexamples in a multi-algorithm verification framework | Physics | 5 | Active |
| US7093218B2 | Incremental, assertion-based design verification | Physics | 5 | Expired |
Source: USPTO / EPO open patent data. Inventor disambiguation is heuristic; counts are objective bibliographic measures.