Separate memory controllers to access data in memory
US10691344B2 · kind B2 · utility
1Cited by
7References
20Claims
0Family size
Assignee
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Key dates
| Filing date | May 30, 2013 |
| Grant date | Jun 23, 2020 |
| Priority date | — |
| Expiry date | Aug 7, 2033 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F13/4243
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A first memory controller receives an access command from a second memory controller, where the access command is timing non-deterministic with respect to a timing specification of a memory. The first memory controller sends at least one access command signal corresponding to the access command to the memory, wherein the at least one access command signal complies with the timing specification. The first memory controller determines a latency of access of the memory. The first memory controller sends feedback information relating to the latency to the second memory controller.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.