Block floating point computations using reduced bit-width vectors
US10691413B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | May 4, 2018 |
| Grant date | Jun 23, 2020 |
| Priority date | — |
| Expiry date | May 4, 2038 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06N3/04
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A system for block floating point computation in a neural network receives a block floating point number comprising a mantissa portion. A bit-width of the block floating point number is reduced by decomposing the block floating point number into a plurality of numbers each having a mantissa portion with a bit-width that is smaller than a bit-width of the mantissa portion of the block floating point number. One or more dot product operations are performed separately on each of the plurality of numbers to obtain individual results, which are summed to generate a final dot product value. The final dot product value is used to implement the neural network. The reduced bit width computations allow higher precision mathematical operations to be performed on lower-precision processors with improved accuracy.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.