Multiple reset types in a system
US10691576B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Sep 26, 2017 |
| Grant date | Jun 23, 2020 |
| Priority date | — |
| Expiry date | Mar 31, 2038 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2201/87
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An integrated circuit can include a functional unit and a local debug unit. The local debug unit can include a trace buffer, and the local debug unit is configured to track and store operation information of the functional unit in the trace buffer. The integrated circuit can also include a global debug unit coupled to the local debug unit. The integrated circuit is configured to send a debug reset command to reset the functional unit, without sending the debug reset command to the local debug unit, thereby retaining information stored in the trace buffer. The integrated circuit is also configured to send a power-up reset command to reset the local debug unit and the functional unit, thereby causing the local debug unit to clear the trace buffer.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.