Semiconductor memory device, memory system, and refresh method thereof
US10692561B2 · kind B2 · utility
2Cited by
9References
19Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Jul 11, 2018 |
| Grant date | Jun 23, 2020 |
| Priority date | — |
| Expiry date | Aug 29, 2038 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04N25/773
- WIPO fieldAudio-visual technology
- WIPO sectorElectrical engineering
Abstract
A semiconductor memory device includes a cell array that includes a plurality of DRAM cells to store data, and refresh control logic that refreshes the plurality of DRAM cells depending on access scenario information provided from an outside. The refresh control logic determines a refresh time of the plurality of DRAM cells with reference to the access scenario information and a retention characteristic of the plurality of DRAM cells and refreshes the plurality of DRAM cells depending on the determined refresh time.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.