Controlling aggregate signal amplitude from device arrays by segmentation and time-gating
US10692573B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Sep 10, 2019 |
| Grant date | Jun 23, 2020 |
| Priority date | — |
| Expiry date | Sep 10, 2039 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2213/79
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
High dynamic range resistive arrays are provided. An array of resistive elements provides a vector of current outputs equal to the analog vector-matrix product between (i) a vector of voltage inputs to the array encoding a vector of analog input values and (ii) a matrix of analog resistive weights within the array. First stage current mirrors are electrically coupled to a subset of the resistive elements through a local current accumulation wire. A second stage current mirror is electrically coupled to the first stage current mirrors through a global accumulation wire. Each of the first stage current mirrors includes at least one component having respective scaling factors selectable to scale up or down the current in the local current accumulation wire, thus controlling the aggregate current on the global accumulation wire.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.