Pritish Narayanan
24Patents
1h-index
24Co-inventors
49Inventor score
Filing activity: Aug 15, 2016 → Dec 2, 2022
Most-cited inventions
| Patent | Title | Area | Cited by | Status |
|---|---|---|---|---|
| US10453528B1 | Controlling aggregate signal amplitude from device arrays by segmentation and time-gating | Physics | 4 | Active |
| US11038520B1 | Analog-to-digital conversion with reconfigurable function mapping for neural networks activation function acceleration | Electricity | 1 | Active |
| US11184245B2 | Configuring computing nodes in a three-dimensional mesh topology | Electricity | 1 | Active |
| US11461640B2 | Mitigation of conductance drift in neural network resistive processing units | Physics | 1 | Active |
| US11580373B2 | System, method and article of manufacture for synchronization-free transmittal of neuron values in a hardware artificial neural networks | Physics | 1 | Active |
| US10423877B2 | High memory bandwidth neuromorphic computing system | Electricity | 1 | Active |
| US11646944B2 | Configuring computing nodes in a three-dimensional mesh topology | Electricity | 0 | Active |
| US11386320B2 | Magnetic domain wall-based non-volatile, linear and bi-directional synaptic weight element | Electricity | 0 | Active |
| US11562240B2 | Efficient tile mapping for row-by-row convolutional neural network mapping for analog artificial intelligence network inference | Physics | 0 | Active |
| US12003240B1 | Analog memory-based complex multiply-accumulate (MACC) compute engine | Physics | 0 | Active |
| US11182673B2 | Temporal memory adapted for single-shot learning and disambiguation of multiple predictions | Physics | 0 | Active |
| US12019590B2 | System, method and article of manufacture for synchronization-free transmittal of neuron values in a hardware artificial neural networks | Physics | 0 | Active |
| US11347999B2 | Closed loop programming of phase-change memory | Physics | 0 | Active |
| US11823740B2 | Selective application of multiple pulse durations to crossbar arrays | Physics | 0 | Active |
| US11868893B2 | Efficient tile mapping for row-by-row convolutional neural network mapping for analog artificial intelligence network inference | Physics | 0 | Active |
| US11488664B2 | Distributing device array currents across segment mirrors | Physics | 0 | Active |
| US11977974B2 | Compression of fully connected / recurrent layers of deep network(s) through enforcing spatial locality to weight matrices and effecting frequency compression | Physics | 0 | Active |
| US10692573B2 | Controlling aggregate signal amplitude from device arrays by segmentation and time-gating | Physics | 0 | Active |
| US11056185B2 | Apparatus for deep learning operations on resistive crossbar array | Physics | 0 | Active |
| US11514981B1 | Programming devices and weights in hardware | Physics | 0 | Active |
| US11436479B2 | System and method for transfer of analog synaptic weight information onto neuromorphic arrays with non-ideal non-volatile memory device | Physics | 0 | Active |
| US12050997B2 | Row-by-row convolutional neural network mapping for analog artificial intelligence network training | Physics | 0 | Active |
| US12255656B2 | Split pulse width modulation to reduce crossbar array integration time | Physics | 0 | Active |
| US11797833B2 | Competitive machine learning accuracy on neuromorphic arrays with non-ideal non-volatile memory devices | Physics | 0 | Active |
Source: USPTO / EPO open patent data. Inventor disambiguation is heuristic; counts are objective bibliographic measures.