Integrated circuit, construction of integrated circuitry, and method of forming an array
US10692727B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jul 24, 2018 |
| Grant date | Jun 23, 2020 |
| Priority date | — |
| Expiry date | Jul 24, 2038 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2223/5446
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method of forming an array comprising using two different composition masking materials in forming a pattern of spaced repeating first features of substantially same size and substantially same shape relative one another. A pattern-interrupting second feature of at least one of different size or different shape compared to that of the first features is within and interrupts the pattern of first features. The pattern of the first features with the pattern-interrupting second feature are translated into lower substrate material that is below the first features and the pattern-interrupting second feature. Material of the first features and of the pattern-interrupting second feature that is above the lower substrate material is removed at least one of during or after the translating. After the removing, the pattern-interrupting second feature in the lower substrate material is used as a reference location to reckon which of the two different composition masking materials was used to make first spaces between the first features in an analysis area in the material that was above the lower substrate material or which of the two different composition masking materials was used to make se…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.