Geometry for threshold voltage tuning on semiconductor device
US10692770B2 · kind B2 · utility
2Cited by
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Key dates
| Filing date | May 30, 2018 |
| Grant date | Jun 23, 2020 |
| Priority date | — |
| Expiry date | May 30, 2038 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D84/0128
Abstract
Semiconductor device structures having gate structures with tunable threshold voltages are provided. Various geometries of device structure can be varied to tune the threshold voltages. In some examples, distances from tops of fins to tops of gate structures can be varied to tune threshold voltages. In some examples, distances from outermost sidewalls of gate structures to respective nearest sidewalls of nearest fins to the respective outermost sidewalls (which respective gate structure overlies the nearest fin) can be varied to tune threshold voltages.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.