Semiconductor device combining passive components with HEMT
US10692857B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | May 8, 2018 |
| Grant date | Jun 23, 2020 |
| Priority date | — |
| Expiry date | May 8, 2038 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D30/475
- WIPO fieldElectrical machinery, apparatus, energy
- WIPO sectorElectrical engineering
Abstract
A semiconductor structure includes a substrate, a first III-V compound layer, a second III-V compound layer, a third III-V compound layer, and a fourth III-V compound layer. The top of the substrate includes a first region and a second region. The first III-V compound layer is in the first region. The second III-V compound layer is disposed over the first III-V compound layer. A first carrier channel is formed between the first III-V compound layer and the second III-V compound layer. The second III-V compound layer has a first thickness. The third III-V compound layer is in the second region. The fourth III-V compound layer is disposed over the third III-V compound layer. A second carrier channel is formed between the fourth III-V compound layer and the third III-V compound layer. The fourth III-V compound layer has a second thickness less than the first thickness.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.