Semiconductor memory device and method of manufacturing the same
US10692881B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | May 17, 2018 |
| Grant date | Jun 23, 2020 |
| Priority date | — |
| Expiry date | May 17, 2038 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10B43/50
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A semiconductor memory device includes a body conductive layer that includes a cell array portion and a peripheral circuit portion, an electrode structure on the cell array portion of the body conductive layer, vertical structures that penetrate the electrode structure, a residual substrate on the peripheral circuit portion of the body conductive layer, and a connection conductive pattern penetrating the residual substrate. The electrode structure includes a plurality of electrode that are stacked on top of each other. The vertical structures are connected to the cell array portion of the body conductive layer. The connection conductive pattern is connected to the peripheral circuit portion of the body conductive layer.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.