Multiplier-accumulator circuit, logic tile architecture for multiply-accumulate, and IC including logic tile array
US10693469B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Aug 20, 2019 |
| Grant date | Jun 23, 2020 |
| Priority date | — |
| Expiry date | Aug 20, 2039 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K19/17724
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
An integrated circuit comprising a plurality of multiply-accumulator circuitry interconnected in a concatenation architecture. Each multiply-accumulator circuitry includes first and second MAC circuits and a load-store register. The first MAC circuit includes a multiplier to multiply first data by a first multiplier weight data and generate a first product data, and an accumulator to add first input data and the first product data to generate first sum data. The second MAC circuit includes a multiplier to multiply second data by a second multiplier weight data and generate a second product data, and an accumulator, coupled to the multiplier of the second MAC circuit and the accumulator of the first MAC circuit, to add the first sum data and the second product data to generate second sum data. The load-store register is coupled to the accumulator of the second MAC circuit to temporarily store the second sum data.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.