PLL filter having a capacitive voltage divider
US10693474B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Feb 14, 2019 |
| Grant date | Jun 23, 2020 |
| Priority date | — |
| Expiry date | Feb 14, 2039 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03H7/06
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A phase-locked loop (PLL) includes a detector configured to generate an error signal based on a difference between a reference signal and an output signal, a charge pump configured to generate current pulses based on the error signal, a loop filter configured to generate a control voltage based on the current pulses, and a voltage-controlled oscillator (VCO) configured to generate the output signal at a frequency which is a function of the control voltage. The loop filter includes a capacitive voltage divider configured to reduce the control voltage from a range that falls within a voltage domain of the charge pump to a range that falls within a voltage domain of the VCO, the voltage domain of the charge pump being greater than the voltage domain of the VCO.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.