Gradual frequency transition with a frequency step
US10693475B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | May 31, 2019 |
| Grant date | Jun 23, 2020 |
| Priority date | — |
| Expiry date | May 31, 2039 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03L7/235
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A method for generating a clock signal by a phase-locked loop includes generating a phase difference signal based on an input clock signal and a feedback clock signal and generating a loop filter output signal. In a first mode, the loop filter output signal is generated based on the phase difference signal and a predetermined frequency slope, and may include generating a phase-slope-limited version of the phase difference signal based on a predetermined phase slope limit and generating a frequency-slope-limited version of the phase difference signal based on the predetermined frequency slope limit. In a second mode, the loop filter output signal may be generated based on the predetermined frequency slope limit, a value of the loop filter output signal, and a target frequency. In the second mode, the loop filter output signal may be generated further based on a predetermined frequency step value.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.