Pipelined analog-to-digital converter calibration
US10693484B1 · kind B1 · utility
0Cited by
2References
14Claims
0Family size
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Key dates
| Filing date | Mar 20, 2019 |
| Grant date | Jun 23, 2020 |
| Priority date | — |
| Expiry date | Mar 20, 2039 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03M1/164
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A method and apparatus for calibrating a pipelined analog-to-digital converter (ADC) is disclosed. A method includes reading a first output level from a first sub-ADC, reading one or more additional output levels from one or more additional sub-ADCs, combining the one or more additional output levels from the one or more additional sub-ADCs into a combined output level, and adjusting a comparator threshold of the first sub-ADC when the first output level and the combined output level meet a set of predetermined conditions.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.