Current regulation for accurate and low-cost voltage measurements at the wafer level
US10698020B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Mar 26, 2014 |
| Grant date | Jun 30, 2020 |
| Priority date | — |
| Expiry date | May 20, 2038 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG01R31/2851
- WIPO fieldMeasurement
- WIPO sectorInstruments
Abstract
A test system and test techniques for accurate high current parametric testing of semiconductor devices. In operation, the test system supplies a current to the semiconductor device and measures a voltage on the device. The testing system may use the measured voltage to compute an ON resistance for the high-current semiconductor device. In one technique, multiple force needles contact a pad in positions that provide equi-resistant paths to one or more sense needles contacting the same pad. In another technique, current flow through the force needles is regulated such that voltage at the pad of the device under test is representative of the ON resistance of the device and independent of contact resistance of the force needle. Another technique entails generating an alarm indication when the contact resistance of a force needle exceeds a threshold.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.