Trailing or leading digit anticipator
US10698660B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jun 3, 2019 |
| Grant date | Jun 30, 2020 |
| Priority date | — |
| Expiry date | Jun 3, 2039 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F7/74
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Methods and leading zero anticipators for estimating the number of leading zeros in a result of a fixed point arithmetic operation which is accurate to within one bit for any signed fixed point numbers. The leading zero anticipator includes an input encoding circuit which generates an encoded input string from the fixed point numbers; a window-based surrogate string generation circuit which generates a surrogate string whose leading one is an estimate of the leading one in the result of the arithmetic operation by examining consecutive windows of the encoded input string and setting corresponding bits of the surrogate string based on the examinations; and a counter circuit configured to estimate the number of leading zeros in the result of the arithmetic operation based on the leading one in the surrogate string.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.