Timing optimization of memory blocks in a programmable IC
US10699053B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Jan 17, 2018 |
| Grant date | Jun 30, 2020 |
| Priority date | — |
| Expiry date | Jun 10, 2038 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2119/12
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Methods and apparatus for implementing a circuit design are provided. A physical description is generated corresponding to a predefined physical layout of a programmable integrated circuit. The circuit design includes a memory block. A timing analysis is executed to determine a first timing profile of the physical description. The physical description is optimized (or at least altered), and a physical implementation is generated based on the optimized physical description. Optimizing the physical description includes: selectively moving from or into the memory block of the physical description a register in response to an attribute of the memory block; executing a timing analysis to determine a second timing profile of the physical description with the register moved from or into the memory block of the physical description; comparing the first and second timing profiles; and selectively accepting or reversing the moving based on the comparison of the first and second timing profiles.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.