Word line decoder memory architecture
US10699761B2 · kind B2 · utility
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203References
9Claims
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Key dates
| Filing date | Sep 18, 2018 |
| Grant date | Jun 30, 2020 |
| Priority date | — |
| Expiry date | Sep 18, 2038 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C13/0028
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A clocked driver circuit can include a level shifter latch and a driver. The level shifter latch can be configured to receive an input signal upon a clock signal and generate a level shifted output signal. The driver can be configured to receive the level shifted output signal from the level shifter and drive the output signal on a line. The signal levels of the output signal can be greater than the signal level of the input signal.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.