Semiconductor test structure and method for forming the same
US10699973B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Nov 6, 2017 |
| Grant date | Jun 30, 2020 |
| Priority date | — |
| Expiry date | Nov 6, 2037 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2223/5446
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A test structure for semiconductor chips of a wafer, and the method of forming the same is included. The test structure may include a first portion disposed within a corner area of a first chip on the wafer, and at least another portion disposed within another corner of another chip on the wafer, wherein before dicing of the chips, the portions form the test structure. The test structure may include an electronic test structure or an optical test structure. The electronic test structure may include probe pads, each probe pad positioned across two or more corner areas of two or more chips. The corner areas including the test structures disposed therein may be removed from the chips during a dicing of the chips.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.