Method of detecting delamination in an integrated circuit package structure
US10699977B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jul 8, 2019 |
| Grant date | Jun 30, 2020 |
| Priority date | — |
| Expiry date | Jul 8, 2039 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/3511
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method of detecting delamination in an integrated circuit package structure, the method includes forming a plurality of through vias over a carrier substrate; placing a device die over the carrier substrate and between the through vias, wherein the device die comprises a metal pillar; forming a molding material surrounding the device die and the through vias; forming a testing metal line extending along a top surface of the molding material and past an interface between the device die and the molding material; applying a current to the testing metal line; detecting an electrical signal of the testing metal line during the applying the current to the testing metal line; and determining, based on the detected electrical signal of the testing metal line, whether a delamination occurs between the device die and the molding material.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.