Isolator with symmetric multi-channel layout
US10699995B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | May 9, 2018 |
| Grant date | Jun 30, 2020 |
| Priority date | — |
| Expiry date | May 16, 2038 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2224/49175
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
An integrated circuit isolation product includes a first integrated circuit die. The first integrated circuit die includes a first terminal and a second terminal adjacent to the first terminal. The first terminal and the second terminal are configured as a differential pair of terminals configured to communicate a differential signal across an isolation barrier. The first integrated circuit die includes at least one additional terminal adjacent to the differential pair of terminals. The at least one additional terminal is disposed symmetrically with respect to the differential pair of terminals. The first terminal may have a first parasitic capacitance and the second terminal may have a second parasitic capacitance. The first parasitic capacitance may be substantially the same as the second parasitic capacitance. The at least one additional terminal may be disposed symmetrically with respect to a line of symmetry for the differential pair of terminals.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.