Packaging device and method of making the same
US10700033B2 · kind B2 · utility
0Cited by
15References
20Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Aug 13, 2018 |
| Grant date | Jun 30, 2020 |
| Priority date | — |
| Expiry date | Aug 13, 2038 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/15311
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
The present disclosure relates a method of forming an integrated chip packaging device. In some embodiments, the method may be performed by forming a conductive trace on a surface of a packaging component. The conductive trace has an angled surface defining an undercut. A molding material is deposited over an entirety of the conductive trace and within the undercut. The molding material is removed from an upper surface of the conductive trace. The molding material has a sloped outermost sidewall after removing the molding material from the upper surface. A solder region is formed on the upper surface of the conductive trace.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.