Leakage current reduction in electrical isolation gate structures
US10700065B2 · kind B2 · utility
4Cited by
5References
19Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Oct 10, 2018 |
| Grant date | Jun 30, 2020 |
| Priority date | — |
| Expiry date | Oct 10, 2038 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D84/0158
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
In an embodiment, an integrated circuit includes transistors in different active regions, electrically isolated using single diffusion break isolation. The single diffusion break isolation includes a first dummy transistor that has a different threshold voltage than the transistors in either active region for which the single diffusion break is creating isolation. The first dummy transistor may have lower leakage current than transistors in either active region, creating effective isolation between the active regions and consuming relatively small amounts of power due to the lower leakage currents.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.