Random bit cell with memory units
US10700080B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jul 17, 2019 |
| Grant date | Jun 30, 2020 |
| Priority date | — |
| Expiry date | Jul 17, 2039 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10B41/10
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A random bit cell includes a random bit cell. The random bit cell includes a volatile memory unit, a first non-volatile memory unit, a second non-volatile memory unit, a first select transistor, and a second select transistor. The first non-volatile memory unit is coupled to a first data terminal of the volatile memory unit, and the second non-volatile memory unit is coupled to a second data terminal of the volatile memory unit. The first select transistor has a first terminal coupled to the first data terminal of the volatile memory unit, a second terminal coupled to a first bit line, and a control terminal coupled to a word line. The second select transistor has a first terminal coupled to the second data terminal of the volatile memory unit, a second terminal coupled to a second bit line, and a control terminal coupled to a word line.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.