Memory device and a method for forming the memory device
US10700277B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Feb 1, 2019 |
| Grant date | Jun 30, 2020 |
| Priority date | — |
| Expiry date | Feb 1, 2039 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10N70/8833
Abstract
A memory device may include a bottom electrode, first and second switching elements over the bottom electrode, and first and second top electrodes over the first and second switching elements respectively. The first and second top electrodes may include first and second contact surfaces in contact with the first and second switching elements respectively. The first and second switching elements may each have a resistance configured to switch between resistance values in response to changes in voltages applied between the top electrodes and the bottom electrode. The bottom electrode may include at least one conductive layer having third and fourth contact surfaces in contact with the first and second switching elements respectively. An area of the first contact surface may be greater than an area of the third contact surface, and an area of the second contact surface may be greater than an area of the fourth contact surface.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.