Patent · US Active

Low power and low jitter phase locked loop with digital leakage compensation

US10700688B1 · kind B1 · utility

2Cited by

2References

18Claims

0Family size

Assignee

Intel Corporation · US

Inventors

Yongping Fan · Portland, US
Dan Zhang · Fremont, US
Bo Xiang · Nanhu, CN

Key dates

Filing date	Dec 14, 2018
Grant date	Jun 30, 2020
Priority date	—
Expiry date	Dec 14, 2038

Classification

Technology area (CPC G)Physics
CPC primaryG04F10/005
WIPO fieldBasic communication processes
WIPO sectorElectrical engineering

Abstract

Described is a low power and low jitter phase locked loop (PLL) or delay locked loop (DLL) with digital leakage compensation. The compensation is provided by an apparatus which comprises: a circuitry to generate a pulse with a digitally controlled pulse width, wherein the pulse width is proportional to a static phase error of a PLL or a DLL; and a charge pump coupled to the circuitry, wherein the charge pump is to receive the pulse and to source or sink current to or from a node according to the pulse width.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.