CMOS quarter-rate multiplexer for high-speed serial links
US10700888B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Aug 6, 2018 |
| Grant date | Jun 30, 2020 |
| Priority date | — |
| Expiry date | Aug 6, 2038 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04J3/047
- WIPO fieldTelecommunications
- WIPO sectorElectrical engineering
Abstract
Various aspects provide for a multiplexer for high-speed serial links. For example, a system can include a first stage data path multiplexer circuit and a second stage data path multiplexer circuit. The first stage data path multiplexer circuit comprises a first inverter circuit to select a first data signal from a set of data signals and a second inverter circuit to select a second data signal from the set of data signals. The first inverter circuit comprises a first set of inverters and a first set of transmission gates. The second inverter circuit comprises a second set of inverters and a second set of transmission gates. The second stage data path multiplexer circuit is configured as a third inverter circuit to select the first data signal or the second data signal as an output data signal. The third inverter circuit comprises a third set of inverters and a third set of transmission gates.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.