Scalably mechanism to implement an instruction that monitors for writes to an address
US10705961B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Sep 27, 2013 |
| Grant date | Jul 7, 2020 |
| Priority date | — |
| Expiry date | Sep 27, 2033 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2212/1016
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A processor includes a cache-side address monitor unit corresponding to a first cache portion of a distributed cache that has a total number of cache-side address monitor storage locations less than a total number of logical processors of the processor. Each cache-side address monitor storage location is to store an address to be monitored. A core-side address monitor unit corresponds to a first core and has a same number of core-side address monitor storage locations as a number of logical processors of the first core. Each core-side address monitor storage location is to store an address, and a monitor state for a different corresponding logical processor of the first core. A cache-side address monitor storage overflow unit corresponds to the first cache portion, and is to enforce an address monitor storage overflow policy when no unused cache-side address monitor storage location is available to store an address to be monitored.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.