Inventor · Tracy, CA, US

Jeffrey D. Chamberlain

26Patents
4h-index
85Co-inventors
66Inventor score

Filing activity: Dec 30, 2000 → Jan 27, 2023

Most-cited inventions

PatentTitleAreaCited byStatus
US11922220B2 Function as a service (FaaS) system enhancements Physics 29 Active
US10795853B2 Multiple dies hardware processors and methods Emerging Cross-Sectional Technologies 8 Active
US9418009B2 Inclusive and non-inclusive tracking of local cache lines to avoid near memory reads on cache line memory writes into a two level system memory Physics 5 Active
US6883089B2 Method and apparatus for processing a predicated instruction using limited predicate slip Physics 5 Expired
US9619396B2 Two level memory full line writes Physics 4 Active
US10089229B2 Cache allocation with code and data prioritization Physics 3 Active
US9921989B2 Method, apparatus and system for modular on-die coherent interconnect for packetized communication Physics 3 Active
US9563564B2 Cache allocation with code and data prioritization Physics 2 Active
US8868951B2 Multiple-queue multiple-resource entry sleep and wakeup for power savings and bandwidth conservation in a retry based pipeline Emerging Cross-Sectional Technologies 2 Active
US10338974B2 Virtual retry queue Physics 1 Active
US9606925B2 Method, apparatus and system for optimizing cache memory transaction handling in a processor Emerging Cross-Sectional Technologies 1 Active
US9207753B2 Multiple-queue multiple-resource entry sleep and wakeup for power savings and bandwidth conservation in a retry based pipeline Emerging Cross-Sectional Technologies 1 Active
US10339060B2 Optimized caching agent with integrated directory cache Physics 1 Active
US10705961B2 Scalably mechanism to implement an instruction that monitors for writes to an address Physics 0 Active
US11586579B2 Multiple dies hardware processors and methods Emerging Cross-Sectional Technologies 0 Active
US11966330B2 Link affinitization to reduce transfer latency Physics 0 Active
US9436605B2 Cache coherency apparatus and method minimizing memory writeback operations Physics 0 Active
US11899615B2 Multiple dies hardware processors and methods Emerging Cross-Sectional Technologies 0 Active
US12066939B2 Cache line demote infrastructure for multi-processor pipelines Physics 0 Active
US12198186B2 Systems, apparatuses, and methods for resource bandwidth enforcement Physics 0 Active
US10936490B2 System and method for per-agent control and quality of service of shared resources in chip multiprocessor platforms Physics 0 Active
US9189296B2 Caching agent for deadlock prevention in a processor by allowing requests that do not deplete available coherence resources Physics 0 Active
US10204049B2 Value of forward state by increasing local caching agent forwarding Physics 0 Active
US10140213B2 Two level memory full line writes Physics 0 Active
US11294852B2 Multiple dies hardware processors and methods Emerging Cross-Sectional Technologies 0 Active

Source: USPTO / EPO open patent data. Inventor disambiguation is heuristic; counts are objective bibliographic measures.