Supporting adaptive shared cache management
US10705962B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Dec 21, 2017 |
| Grant date | Jul 7, 2020 |
| Priority date | — |
| Expiry date | Dec 31, 2037 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY02D10/00
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Embodiment of this disclosure provides a mechanism to use a portion of an inactive processing element's private cache as an extended last-level cache storage space to adaptively adjust the size of shared cache. In one embodiment, a processing device is provided. The processing device comprising a cache controller is to identify a cache line to evict from a shared cache. An inactive processing core is selected by the cache controller from a plurality of processing cores associated with the shared cache. Then, a private cache of the inactive processing core is notified of an identifier of a cache line associated with the shared cache. Thereupon, the cache line is evicted from the shared cache to install in the private cache.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.