Apparatus and method for chip identification and preventing malicious manipulation of physical addresses by incorporating a physical network with a logical network
US10706177B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jun 30, 2017 |
| Grant date | Jul 7, 2020 |
| Priority date | — |
| Expiry date | Apr 26, 2038 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C13/0059
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A semiconductor device including a semiconductor chip having a cell array is provided. The cell array includes identification cells distributed in sub-blocks of the cell array. The identification cell has a cell address and the sub-block has a block address. The cell address is related to the block address. A portion of the block addresses include the cell address at which an identification cell exhibiting a predetermined characteristic is located. The predetermined characteristic is based on a physical randomness which is intrinsic of the semiconductor chip. The semiconductor chip further has a physical random number code including the portion of the block address. The physical random number code is secured by the semiconductor chip. This disclosure provides the technology to prevent malicious manipulation of physical addresses by artfully incorporating physical network with logical network, and to make the administration of hardware network more secure.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.