Voltage reconciliation in multi-level power managed systems
US10706192B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Mar 30, 2018 |
| Grant date | Jul 7, 2020 |
| Priority date | — |
| Expiry date | Aug 23, 2038 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2119/06
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method and EDA software tool for analyzing and verifying that a multi-level power managed system description (IC design) is free of power-state combination conflicts by way of identifying and reconciling voltage level and power-state combination conflicts caused by reused blocks (IP cores). The reconciliation process involves generating Power-State Tables (PSTs) associated with each hierarchical circuit level (e.g., top/system level and lower/block levels) of the IC design using both initial power supply voltage values and reconciled/revised voltage values, which are determined by the main driver voltage levels of each power supply. Initial supply relationships generated using the initial PSTs are then compared with final supply relationships generated using the reconciled PSTs, whereby conflicts are identified when one or more initial supply relationship fails to match a final supply relationship, or when one or more final supply relationship fails to match an initial supply relationship.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.