Machine learning sparse computation mechanism
US10706498B2 · kind B2 · utility
11Cited by
5References
12Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | May 20, 2019 |
| Grant date | Jul 7, 2020 |
| Priority date | — |
| Expiry date | May 20, 2039 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY02D10/00
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An apparatus to facilitate processing of a sparse matrix is disclosed. The apparatus includes a plurality of processing units each comprising one or more processing elements, including logic to read operands, a multiplication unit to multiply two or more operands and a scheduler to identify operands having a zero value and prevent scheduling of the operands having the zero value at the multiplication unit.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.