Kamal Sinha
122Patents
10h-index
101Co-inventors
75Inventor score
Filing activity: Apr 1, 2017 → Mar 11, 2024
Most-cited inventions
| Patent | Title | Area | Cited by | Status |
|---|---|---|---|---|
| US10474458B2 | Instructions and logic to perform floating-point and integer operations for machine learning | Physics | 40 | Active |
| US10353706B2 | Instructions and logic to perform floating-point and integer operations for machine learning | Physics | 40 | Active |
| US11080046B2 | Instructions and logic to perform floating point and integer operations for machine learning | Physics | 33 | Active |
| US11360767B2 | Instructions and logic to perform floating point and integer operations for machine learning | Physics | 33 | Active |
| US11620256B2 | Systems and methods for improving cache efficiency and utilization | Physics | 32 | Active |
| US11169799B2 | Instructions and logic to perform floating-point and integer operations for machine learning | Physics | 31 | Active |
| US10304154B2 | Coordination and increased utilization of graphics processors during inference | Emerging Cross-Sectional Technologies | 29 | Active |
| US10186011B2 | Programmable coarse grained and sparse matrix compute hardware with advanced scheduling | Physics | 29 | Active |
| US10346944B2 | Machine learning sparse computation mechanism | Emerging Cross-Sectional Technologies | 17 | Active |
| US10706498B2 | Machine learning sparse computation mechanism | Emerging Cross-Sectional Technologies | 11 | Active |
| US10401954B2 | Sensory enhanced augmented reality and virtual reality device | Physics | 10 | Active |
| US11210760B2 | Programmable coarse grained and sparse matrix compute hardware with advanced scheduling | Physics | 7 | Active |
| US10102149B1 | Replacement policies for a hybrid hierarchical cache | Physics | 7 | Active |
| US10417731B2 | Compute optimization mechanism for deep neural networks | Emerging Cross-Sectional Technologies | 6 | Active |
| US10423415B2 | Hierarchical general register file (GRF) for execution block | Emerging Cross-Sectional Technologies | 6 | Active |
| US10444817B2 | System, apparatus and method for increasing performance in a processor during a voltage ramp | Physics | 6 | Active |
| US10410098B2 | Compute optimizations for neural networks | Physics | 5 | Active |
| US10261903B2 | Extend GPU/CPU coherency to multi-GPU cores | Emerging Cross-Sectional Technologies | 5 | Active |
| US10452397B2 | Efficient multi-context thread distribution | Physics | 5 | Active |
| US10983594B2 | Sensory enhanced augmented reality and virtual reality device | Physics | 5 | Active |
| US11360808B2 | Efficient thread group scheduling | Physics | 4 | Active |
| US11145105B2 | Multi-tile graphics processor rendering | Physics | 4 | Active |
| US10346166B2 | Intelligent thread dispatch and vectorization of atomic operations | Emerging Cross-Sectional Technologies | 4 | Active |
| US10909039B2 | Data prefetching for graphics data processing | Emerging Cross-Sectional Technologies | 3 | Active |
| US11074072B2 | Compute optimizations for neural networks using bipolar binary weight | Physics | 3 | Active |
Source: USPTO / EPO open patent data. Inventor disambiguation is heuristic; counts are objective bibliographic measures.