Method and circuit for adaptive read-write operation in self-timed memory
US10706915B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Mar 13, 2019 |
| Grant date | Jul 7, 2020 |
| Priority date | — |
| Expiry date | Mar 13, 2039 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C11/419
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A memory device includes first and second dummy word line portions. A dummy word line driver drives the first dummy word line portion. A voltage dropping circuit causes a voltage on the second dummy word line to be less than a voltage on the first dummy word line. At least one dummy memory cell is coupled to the second dummy word line portion, remains in standby until assertion of the second dummy word line, and performs a dummy cycle in response to assertion of the second dummy word line. A reset signal generation circuit generates a reset signal in response to completion of a dummy cycle by the at least one dummy memory cell. An internal clock signal is generated from an external clock signal and the reset signal and is used in performing a read and/or write cycle to a memory array.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.