Fine line patterning methods
US10707081B2 · kind B2 · utility
2Cited by
0References
18Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Nov 1, 2018 |
| Grant date | Jul 7, 2020 |
| Priority date | — |
| Expiry date | Nov 1, 2038 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L21/76885
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method of manufacturing a semiconductor device including operations of forming a first hard mask over an underlying layer on a substrate by a photolithographic and etching method, forming a sidewall spacer pattern having a first sidewall portion and a second sidewall portion on opposing sides of the first hard mask, etching the first sidewall portion, etching the first hard mask and leaving the second sidewall portion bridging a gap of the etched first hard mask, and processing the underlying layer using the second hard mask.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.