Patent · US Active

MOSFET with reduced resistance

US10707327B2 · kind B2 · utility

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16Claims

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Assignee

Great Wall Semiconductor Corporation · US

Inventors

Patrick M. Shea · Oviedo, US
David N. Okada · Chandler, US
Samuel J. Anderson · Wallingford, US

Key dates

Filing date	Dec 28, 2015
Grant date	Jul 7, 2020
Priority date	—
Expiry date	Aug 12, 2037

Classification

Technology area (CPC H)Electricity
CPC primaryH10D64/257
WIPO fieldSemiconductors
WIPO sectorElectrical engineering

Abstract

A semiconductor device includes a semiconductor substrate including a doped region. A metal layer is formed on the doped region. An insulating layer covers the metal layer. The metal layer can serve as a buried metal layer which reduces electrical resistance between electrical charge in the doped region and adjacent contacts. The contacts can extend through the insulating layer between the buried metal layer and overlying metal stripes.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.