Transistor with a negative capacitance and a method of creating the same
US10707347B2 · kind B2 · utility
3Cited by
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20Claims
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Assignee
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Key dates
| Filing date | Jan 23, 2019 |
| Grant date | Jul 7, 2020 |
| Priority date | — |
| Expiry date | Jan 23, 2039 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D84/038
Abstract
The various described embodiments provide a transistor with a negative capacitance, and a method of creating the same. The transistor includes a gate structure having a ferroelectric layer. The ferroelectric layer is formed by forming a thick ferroelectric film, annealing the ferroelectric film to have a desired phase, and thinning the ferroelectric film to a desired thickness of the ferroelectric layer. This process ensures that the ferroelectric layer will have ferroelectric properties regardless of its thickness.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.