MOS power transistors in parallel channel configuration
US10707856B2 · kind B2 · utility
0Cited by
3References
20Claims
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Key dates
| Filing date | Sep 19, 2017 |
| Grant date | Jul 7, 2020 |
| Priority date | — |
| Expiry date | Jul 20, 2038 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH02H3/05
- WIPO fieldElectrical machinery, apparatus, energy
- WIPO sectorElectrical engineering
Abstract
A circuit comprises a first metal-oxide semiconductor, MOS, power transistor having a first gate terminal, a first drain terminal, and a first source terminal, a second MOS power transistor having a second gate terminal, a second drain terminal, and a second source terminal, and a switch connected in-between the first gate terminal and the second gate terminal and configured to selectively couple the first gate terminal and the second gate terminal.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.